Silicon wafer polishing is an important step in manufacturing semiconductor devices, micro-electro mechanical systems (MEMS), micro-optical devices, and similar micro-scale devices manufactured on a substrate. Polishing the wafer provides the mirror-like and very flat surface required for the fabrication of micro-scale devices. Conventionally, wafer polishing is a multi-step process using a slurry containing abrasives, and chemical mixtures, such as acids. The wafer is secured on a turntable and is rotated. Polishing heads, such as pads, brushes, sponges, etc. press on the rotating wafer. A combination of chemical and mechanical effects polish the wafer. This type of polishing, known as chemical-mechanical polishing, or “CMP”, has been widely used for over 30 years.
In practice, polishing can be a complex process presenting many challenges and complications. Changes in various polishing parameters, including spin speed, pressure, time, slurry composition, wafer flatness, pad wear, uniformity of loading, etc. can affect the outcome. In addition, these chemical/mechanical processes generally require several remedial follow on steps, to reduce stresses in the wafer created by the polishing step, or to remove slurry particles or other contamination caused by the polishing step. Moreover, wafer polishing can be time consuming in the manufacturing process. While extensive research and development efforts have concentrated on trying to reduce these disadvantages, especially in the semiconductor industry, the basic underlying problems with CMP remain. Accordingly, while CMP and other existing polishing technology has achieved various successes, there is vast need for improved polishing techniques.